Chiplets, Made Practical

UCIe™ is a trademark of the UCIe Consortium. This project is not affiliated with or endorsed by the UCIe Consortium.

The Problem We're Trying to Solve

Chiplet technology is becoming the standard way to build complex chips. Instead of one monolithic die, modern designs connect multiple smaller dies — CPU, memory, accelerator — through standardized interconnects like UCIe™ (Universal Chiplet Interconnect Express).

But for students and startups, getting started with chiplets is hard:

• Existing implementations use complex build systems or unfamiliar languages
• Documentation assumes prior expertise with the protocol
• There's no simple "starting point" to learn and experiment

We reviewed what's available in the open-source ecosystem — UC Berkeley's Chisel-based implementation, Zero ASIC's Switchboard framework, CHIPS Alliance's AIB PHY. Each has value, but none offered a straightforward SystemVerilog foundation that someone could pick up, read, and extend.

So we built one.

What We Built

We created a UCIe D2D adapter in SystemVerilog, along with basic verification infrastructure. The goal was to make something readable, runnable, and extensible.

We split it into two parts: the IP (the actual design) and the VIP (verification components). Both are needed to understand how the protocol works.

The IP Side

Component	What It Does
ucie_ltssm.sv	Link training state machine — brings up the connection
ucie_sideband.sv	Parameter negotiation between dies
ucie_mainband_crc.sv	512-bit datapath with CRC-32 protection
tilelink_ucie_adapter.sv	Bridge to RISC-V ecosystem
axi_ucie_adapter.sv	Bridge to ARM ecosystem
cxl_ucie_adapter.sv	Bridge to CXL memory/IO
aib_wrapper.sv	Behavioral PHY model for simulation

The VIP Side

Verification is how you know things work. We included:

• Driver & Monitor — inject transactions, observe responses
• Checker & Scoreboard — compare expected vs actual
• SVA Assertions — catch protocol violations
• Spec-rule Checker (partial) — validate against select UCIe-like rules
• Functional Coverage — track what's been tested

What's NOT Included

We want to be clear about what this isn't:

• Not UCIe™ compliant — This implementation is not certified or validated by the UCIe Consortium. We implemented core protocol concepts based on publicly available information, not every specification requirement.
• No real analog PHY — The AIB wrapper is behavioral. Real PHY needs foundry PDK and analog design.
• No retry/recovery — Error recovery logic is not implemented.
• Not production-hardened — This hasn't been through the rigor needed for tape-out.

This is a learning tool and starting point, not a finished product.

Where We're Going

The real value of chiplets is connecting multiple dies. We're building toward practical demos:

Release Roadmap

We're releasing in phases, each with working demos:

Who This Is For

Students learning chiplet architecture — read the code, run simulations, understand the protocol layer by layer.

Startups exploring multi-die designs — use as a starting point, extend for your specific needs, reduce early prototyping effort.

Verification engineers learning UCIe — study the VIP patterns, compare against your own work, use the compliance checks as reference.

Universities teaching advanced VLSI — ready lab material with working tests and clear structure.

Why We're Doing This

Chiplet technology will become the standard way to build complex chips. The barrier to entry shouldn't be high just because existing resources are scattered or complex.

We reviewed what's available, identified the gaps, and built something to fill them. It's not perfect, but it's a practical starting point.

If this helps students understand UCIe better, or helps startups prototype faster, it's worth sharing.