IN-HOUSE EDA — PART 2

EQWAVE: Timestamps lie. Behavior doesn’t

RTL and GLS have different timing by design. No tool compares them semantically. We're building one.

IN-HOUSE EDA - PART 2

EQWAVE: Timestamps lie. Behavior doesn’t

RTL and GLS have different timing by design. No tool compares them semantically.
We're building one.
WIOWIZ Technologies • January 2026 • 10 min read

1. The Problem

RTL simulation passes. GLS simulation fails. Now what?

You open both VCDs in GTKWave. Side by side. But:

  • Signal names don't match — synthesis renamed data_out to _0847_
  • Timing doesn't match — GLS has gate delays RTL doesn't have
  • Cycle-by-cycle comparison is meaningless

You spend 8 hours scrolling waveforms. Eventually you find it: one signal diverged somewhere, and everything cascaded from there.

This happens on every project. Every GLS debug cycle costs days.

We looked for tools. Nothing exists.

2. The Real Verification Flow

GLS Verification Stages
RTL Golden Reference EQWAVE (hard) GLS Zero-Delay New Golden EQWAVE (easy) GLS + SDF Real Timing Silicon Model TAPE-OUT Signoff Behavioral Structural Timing Final

The key insight: Once RTL vs GLS-zero-delay works, GLS-zero-delay vs GLS+SDF is easier:

Challenge RTL vs GLS Zero-Delay GLS Zero vs GLS+SDF
Signal mapping Hard (names changed) Trivial (same netlist)
Structure Different Identical
What differs Logic + naming Only timing

Solve the first comparison. The rest comes free.

3. Why Timestamp Comparison Fails

RTL and GLS must not match in time. This is physics, not a bug.

RTL vs GLS Waveform Timing
clk RTL valid GLS valid GLS data ↑ edge 3 ↑ edge 4 (gate delay) ↑ edge 5 (more delay) 1 2 3 4 5 6 7 Signals arrive at different times!

When a tool says "Signal A changed at edge 3 in RTL but edge 4 in GLS → MISMATCH" — it's lying. That's expected behavior.

The industry has tolerated this for 30 years. Engineers manually compensate in their heads.

4. The Insight: Patterns, Not Timestamps

Forget timestamps. Forget individual clock cycles.

Compare patterns.

Pattern Matching Concept
RTL Pattern valid↑ → data=0x55 → ready↑ → done Edges: 3, 3, 4, 5 GLS Pattern valid↑ → data=0x55 → ready↑ → done Edges: 5, 6, 7, 8 = ✓ SAME PATTERN Different timing, same behavior

RTL does: valid rises, data becomes 0x55, ready rises, transaction completes.

GLS does the same thing — just at different clock edges.

If the pattern matches, the design is correct. If the pattern diverges, that's where the bug is.

5. What We're Building: Fingerprints

EQWAVE compares fingerprints of signal states.

A fingerprint = all signal values at one moment, hashed.

When any signal changes, capture the state of ALL signals. That's one fingerprint.

Fingerprint Generation
Signal State at Edge N valid = 1 ready = 0 data[7:0] = 0x55 state[1:0] = 01 hash() Fingerprint a3f7c2b1 Fingerprint Sequence F1 → F2 → F3 → F4 → F5 → ...

6. Handling Gate Delay Transients

GLS has more fingerprints than RTL — transient states from signals arriving at different times due to gate delays.

Transient Filtering
RTL: F1 → F2 → F3 → F4 → F5 GLS: F1 → Fx → F2 → Fy → F3 → F4 → F5 Fx, Fy = transients (not in RTL) Filter transients GLS filtered: F1 → F2 → F3 → F4 → F5 ✓ MATCH

GLS fingerprints that don't exist in RTL = transients from gate delays. Filter them out.

What remains should match RTL exactly. Same fingerprints, same order.

7. Real-World Workflow: Selective Dumping

Engineers don't dump 100GB VCDs. They dump:

  • Specific time window — where the failure is suspected
  • Specific modules — not the entire SoC
  • Multiple passes — different resolutions, different focus areas

EQWAVE doesn't need to handle massive files. It needs to handle focused, targeted dumps. That makes signal mapping easier too — fewer signals means less ambiguity.

8. First Real Result

Simple design: counter + FSM + handshake. 12 signals.

═══════════════════════════════════════════════════════════════════════════════
EQWAVE v3 — Fingerprint Edition
═══════════════════════════════════════════════════════════════════════════════
RTL: 16 signals, 190 value changes
GLS: 42 signals, 386 value changes

Signal Mapping: 12 mapped, 4 unmapped

Fingerprints:
RTL: 16 fingerprints (16 unique)
GLS: 19 fingerprints (19 unique)
Common: 13 fingerprints

Sequence Comparison:
RTL filtered: 13 (skipped 3 RTL-only)
GLS filtered: 13 (skipped 6 transients)

✅ SEQUENCES MATCH: 13 common states in same order

═══════════════════════════════════════════════════════════════════════════════
VERDICT: PASS
Alignment: 100%
Time: 0.13s
═══════════════════════════════════════════════════════════════════════════════

RTL had 16 state transitions. GLS had 19. But 13 were common — and they appeared in the same order.

The 6 extra GLS fingerprints were transients from gate delays. Filtered out automatically.

9. What's Hard

Signal Mapping at Scale

With 200+ signals, name matching gets ambiguous:

testbench.uut.cpu_state_exec  →  testbench.uut.cpu_state  (wrong!)
testbench.uut.cpu_state_fetch →  testbench.uut.cpu_state  (collision!)

Multiple RTL signals can't map to one GLS signal. We're still tuning this.

Test Setup Matters More Than The Tool

PicoRV32 test failed with 0% alignment. Not because EQWAVE was wrong — but because RTL and GLS testbenches initialized memory differently. Every mem_rdata differed. Every fingerprint differed.

Garbage in, garbage out. Same lesson every verification engineer learns.

10. Current Status

✓ WORKING

  • VCD streaming parser (260K+ value changes)
  • Clock edge detection
  • Fingerprint generation
  • Transient filtering
  • Sequence comparison
  • Divergence reporting

⏳ IN PROGRESS

  • Signal mapping for complex designs
  • Many-to-one collision prevention
  • Scale testing (2000+ signals)
  • Root cause tracing

11. Known Gaps We're Addressing

Gap Problem
Signal mapping at scale Fuzzy name matching breaks with 200+ signals. Need user-provided mapping or synthesis tool export.
X/Z handling Current X→0 normalization hides real bugs. Need proper 3-value or 4-value logic.
Bit width mismatch Synthesis can change signal widths. Currently we skip mismatched widths.
Strict sequence matching Current subset assumption is too brittle. Need LCS (longest common subsequence) for tolerance.
Memory limits Large VCDs can exceed RAM. Need streaming parser with constant memory.
Actionable errors "FAIL 0%" is useless. Need "FAIL at cycle 1247, last match at 1246, signal X diverged."
User signal selection Engineers want to compare specific signals, not everything in the VCD.
Time window filtering Compare only cycles N to M, not entire simulation.

We're not hiding these. They're on the list.

12. The Honest Position

EQWAVE is not a product. It's a research tool we're building because we need it.

What It Does What It Doesn't Do
Compares behavior patterns Explain why bugs exist
Filters gate delay artifacts Trace back through logic
Reports where sequences diverge Work on broken test setups
Handles selective dumps Parse 100GB VCDs (yet)

The gap we're filling: No tool does semantic RTL-vs-GLS comparison. Formal tools check structure, not simulation. Waveform tools compare timestamps, which is wrong for GLS.

13. Why We're Sharing This

Because GLS debug is painful for everyone.

Because the industry has tolerated timestamp-based comparison for 30 years.

Because if someone else builds this better, the industry wins.

We're not claiming we solved it. We're showing the approach: fingerprints, not timestamps. Patterns, not cycles.

EQWAVE doesn't compare time.
It compares patterns — when time cannot be trusted.

We're building this in public. It's not done. But the direction is right.

Part of our in-house EDA series. Previously: VHE (GPU-accelerated gate simulation)

#semiconductor #EDA #verification #GLS #debug #building-in-public