RISC-V Solution

An automotive RISC-V ADAS platform, safety and AI on one SoC

The ADAS SoC is an automotive-grade RISC-V platform that combines an application compute cluster, a functional-safety island running in lockstep, an on-chip AI engine for perception, and the WIOWIZ sensor-fusion datapath, together with the automotive bus and hardware-security suite. It is architected with ISO 26262 functional safety in mind, so the compute, safety monitoring and perception domains are brought together on a single die as a reference design for next-generation driver assistance.

Architecture

RISC-V Compute and Control Domains (application, safety, management) Application CPU Cluster (RISC-V) application compute cores Safety Island (lockstep RISC-V) ASIL grade monitoring NPU AI Perception on-chip neural engine On-chip Interconnect AXI crossbar Sensor Fusion camera radar LiDAR Automotive I/O CAN-FD LIN SENT TSN Security HSM secure boot, crypto Display engine and DisplayPort Memory Subsystem, DDR Controller and SRAM with ECC

Clean architectural view of the reference SoC. Every block is WIOWIZ RTL on our own RISC-V cores, and internal micro-architecture is not shown.

Specifications

CategoryAutomotive ADAS reference SoC
Application coreRISC-V application cluster
Safety coreRISC-V lockstep safety island
AI engineOn-chip NPU for perception
FusionCamera, radar and LiDAR sensor fusion
Automotive I/OCAN-FD, LIN, SENT, TSN Ethernet
SecurityHardware security module (secure boot, crypto)
DisplayDisplay engine with DisplayPort
MemoryDDR controller, SRAM with ECC
Functional safetyISO 26262 oriented architecture
IP ownershipWIOWIZ IP and WIOWIZ VIP
Design flowWIOWIZ in-house EDA
StatusReference design, in development

RISC-V Architecture

Three RISC-V domains work together on the ADAS SoC, an application cluster for compute, a lockstep safety island for ASIL-grade monitoring, and management, alongside an AI perception engine and the sensor-fusion datapath. The compute domain runs the driver assistance software stack, the safety island watches it in lockstep, and the perception and fusion blocks feed a single tracked view of the road into the platform. It is WIOWIZ IP, with no licensed cores anywhere on the die, architected, implemented and verified with our in-house EDA.

Key Features

Three-domain architecture

Application, management and safety domains run side by side with hardware lockstep on the safety island.

On-chip AI perception

An integrated NPU runs perception workloads in hardware, keeping detection on-die and close to the sensors.

Integrated sensor fusion

The WIOWIZ datapath fuses camera, radar and LiDAR into one tracked view of the vehicle surroundings.

Full automotive bus suite

Native CAN-FD, LIN, SENT and TSN Ethernet connect the SoC to the wider vehicle network.

Hardware security module

An on-chip HSM provides secure boot and crypto services to protect the platform and its data.

WIOWIZ IP and VIP

Zero licensed cores, architected, implemented and verified with WIOWIZ EDA.

Applications

ADAS L2+ Automotive safety Autonomous driving compute Vehicle domain controllers