Design & Verfication
EDA & Autonomous
The Game of Imitation: A Way to Build Consciousness
EDA & Autonomous
Chiplets, Made Practical: A UCIe™ D2D reference implementation for students and startups
EDA & Autonomous
VAI (Virtual AI Inference): What Hardware Engineers See
EDA & Autonomous
VAI (Virtual AI Inference) to Mini-GPT : RTL-Verified Transformer Execution on WZ-NPU
EDA & Autonomous
EQWAVE: Timestamps lie. Behavior doesn’t
EDA & Autonomous
Parallel Region-Based Routing on OpenROAD
EDA & Autonomous
VAIDAS: Real-Time ADAS Inference on VAI Architecture
EDA & Autonomous
Bridging Digital and Photonic Verification
EDA & Autonomous
DFT: The Crucial Gap in Open-Source Chip Design
EDA & Autonomous
FSiMX: Building a Verification Simulator as a Platform
WZ-SPICE Engine Series
WIOWIZ Native SPICE: What Our Analog Simulator Runs Today
WZ-SPICE Engine Series
WIOWIZ uPHY: Coupling FSimX and Native SPICE on a 2.5 Gb/s Recovered-Clock Link
WZ-SPICE Engine Series
WIOWIZ Native SPICE at Scale: An 8T SRAM Compute Macro to 170,240 MOS Devices
SOCVP Series
Boot a complete SoC from one binary
FSiMX Studio Series
RTL Simulation, Debug and Coverage in One Window
SOCVP Series
Three RISC-V cores, one boot, one fabric
FSiMX Studio Series
RISC-V HW/SW Co-Simulation Debug
SOCVP Series
The Catalogue Runs
FSiMX Studio Series
Drag-and-Drop Signals, Trace a Driver to Source
SOCVP Series
Architecture is not a directory listing
FSiMX Studio Series
Protocol Transaction and Memory Viewers
SOCVP Series
Compose. Boot. Repeat.
FSiMX Studio Series
Every Coverage Metric in One Database
FSiMX Studio Series
Formal Reachability and UNR Closure
FSiMX Studio Series
Power-Aware Coverage from UPF Intent
FSiMX Engine Series
Why FSimX Built Its Own SystemVerilog Front End
FSiMX Engine Series
Can an Open Simulator Run a Real UVM Environment?
FSiMX Engine Series
What Does Two-State Simulation Hide?
FSiMX Engine Series
An Assertion That Wasn’t Evaluated Did Not Pass
FSiMX Engine Series
How FSimX Decides When Compiled Execution Is Safe
FSiMX Engine Series