1. What is FSiMX
An event-driven functional verification simulator we built in-house.
What the beta supports:
- Verilog / SystemVerilog (IEEE 1800-2017 subset, via Slang frontend)
- UVM basics (build/connect/run phases, sequences, scoreboard)
- ISS mode (RISC-V instruction set simulation + RTL co-simulation)
- PSS-Lite (portable stimulus, intent to test generation)
- CDC static analysis (clock domain crossing checks)
- UPF static checks (power intent, IEEE 1801)
- Netlist simulation with SDF timing annotation
- Gate-level primitives
- Compiled backend (IR to C++ to native execution)
- Multi-threaded simulation kernel
- 276 diagnostic rules with IEEE references
Try it now
git clone https://gitlab.com/wiowiztechnologies/fsimx_beta.git cd fsimx_beta export PATH=$PWD/bin:$PATH bash examples/run_all_examples.sh
2. How It Works
When you run fsxrun, the design passes through a six-stage
pipeline. Slang handles IEEE 1800-2017 parsing. Everything after is ours.
Value model: dual-bit encoding (value_bits + xz_bits).
SimValue supports 256-bit signals with carry-propagating arithmetic. The
scheduler implements IEEE 1800 region ordering (Active, Inactive, NBA, Monitor)
with delta cycle handling and a #0 iteration cap at 1000.
3. What It Looks Like
Real terminal output from the beta. Nothing edited.
3a. Simulation Log
TOOL: fsxrun 0.5.0-beta: Started on Mar 15, 2026 at 06:35:11 IST fsxrun: 0.5.0-beta: (c) Copyright 2025-2026 WioWiz Technologies Pvt Ltd. file: counter.v file: tb_counter.v module worklib.tb_counter:sv errors: 0, warnings: 0 module worklib.counter:sv errors: 0, warnings: 0 Caching library 'worklib' ....... Done Compiled 2 design units from 2 files. 0 errors, 0 warnings. Elaborating the design hierarchy: Top level design units: tb_counter Design hierarchy summary: Instances Unique Modules: 2 2 Registers: 8 8 Always blocks: 2 2 Initial blocks: 2 2 Simulation timescale: 1ns/1ps Elaboration complete. 0 errors, 0 warnings. --- Instance Hierarchy --- tb_counter (tb_counter) Nets: 4 (3 logic, 1 wire) uut (counter) Ports: 4 (3 input, 1 output, 0 inout) Nets: 4 (4 logic) --- Simulation Start --- PASS: counter test --- Simulation Complete --- $finish at time 246 ns --- Simulation Summary --- Design: worklib.tb_counter:sv Sim time: 246 ns Events: 106 total, 54 delta cycles Sim speed: 51484 ns/s (22.2 kHz event rate) Peak memory: 47 MB TOOL: fsxrun 0.5.0-beta: Exiting (total: 00:00:00)
3b. UVM, Full Phase Execution
FSiMX discovers UVM classes, builds the component hierarchy, and walks every phase from build through final. This is real UVM simulation, not parsing, not elaboration. Simulation.
--- UVM Analysis --- UVM classes discovered: 10 Class Base Category fifo_txn uvm_sequence_item sequence_item fifo_fill_drain_seq uvm_sequence sequence fifo_driver uvm_driver driver fifo_monitor uvm_monitor monitor fifo_scoreboard uvm_scoreboard scoreboard fifo_agent uvm_agent agent fifo_env uvm_env env fifo_test uvm_test test --- UVM Topology --- uvm_test_top (fifo_test) env (fifo_env) agt (fifo_agent) drv (fifo_driver) mon (fifo_monitor) sqr (__uvm_sequencer) scb (fifo_scoreboard) --- UVM Phase: build --- [UVM] build_phase: uvm_test_top (fifo_test) [UVM] -> executing real fifo_test::build_phase() [UVM] create uvm_test_top.env (fifo_env) [UVM] create env.agt (fifo_agent) [UVM] create env.scb (fifo_scoreboard) --- UVM Phase: run --- [UVM] -> executing real fifo_test::run_phase() for uvm_test_top --- UVM Phase: report --- [UVM] -> executing real fifo_scoreboard::report_phase() for scb UVM_INFO @ 120ns: uvm_test_top [TEST] ========== TEST PASSED ========== --- UVM Report Summary --- UVM_INFO : 2 UVM_WARNING : 0 UVM_ERROR : 0 UVM_FATAL : 0 TEST PASSED $finish at time 120 ns VCD: fifo_uvm.vcd (1.9 KB, 31 vars, 24 timestamps)
3c. ISS, RISC-V Co-Simulation
FSiMX includes an instruction set simulator for RV32IM. Load an ELF, execute natively, co-simulate with RTL peripherals.
TOOL: fsxrun 0.5.0-beta ISS standalone mode (WM1 RV32IM) ELF: add-01.wm1.elf Entry: 0x00000000 --- ISS Simulation Start --- --- ISS Simulation Complete --- Status: HALTED PC: 0x00003328 Instructions: 3267 Cycles: 3267 Traps: 0 Wall time: 0.000 s Performance: 13.4 MIPS Peak memory: 51 MB
3d. CDC, Clock Domain Crossing Detection
[CDC] Found 2 clock domains: clk_a (1 signals), clk_b (3 signals)
[CDC] Detected 1 crossing between 2 domains
[CDC] 1 unsynchronized crossing remain
WARN: FSX-L1100: signal_a [IEEE 1800-2017 §9.2.2.3]
── Diagnostic Summary ──────────────────────────────
Errors: 0
Warnings: 1
────────────────────────────────────────────────────
3e. Diagnostic Engine
276 rules. IEEE section references. Waivable with +suppress+.
Explainable with --explain.
Rule: FSX-L1100 Severity: WARNING Category: cdc Spec: IEEE 1800-2017 §9.2.2.3 Summary: Signal crosses clock domain without synchronizer Format: signal '%s' driven by clock '%s' sampled by clock '%s' with no synchronizer detected Default: enabled Waivable: yes (+suppress+FSX-L1100)
3f. Gate-Level Simulation with SDF
A 4-bit counter synthesized to standard cells (XOR, AND, BUF, DFF). SDF timing annotation. 17 cycles verified with correct count sequence.
Compiled 12 design units from 3 files.
Design hierarchy summary:
Modules: 13 instances, 12 unique
Registers: 53
Cont. assigns: 17
--- Instance Hierarchy ---
tb_counter4_sdf_typ
dut (counter4_netlist)
u_xor0 (XOR2_X1) u_carry0 (BUF_X1)
u_xor1 (XOR2_X1) u_carry1 (AND2_X1)
u_xor2 (XOR2_X1) u_carry2 (AND2_X1)
u_xor3 (XOR2_X1)
u_ff0..u_ff3 (DFF_X1)
cycle 0: count = 1 (OK)
cycle 7: count = 8 (OK)
cycle 15: count = 0 (OK) wraparound
cycle 16: count = 1 (OK)
SDF-TYP GLS: PASS (17 cycles verified)
4. Tested on Real Designs
Included in Beta (you can verify)
| Design | Type | Result |
|---|---|---|
| PicoRV32 RISC-V CPU | CPU + memory | PASS (272 transactions) |
| 29 example designs | Verilog, SV, UVM, stress | 29/29 PASS |
| 5 UVM testbenches | FIFO, SPI, ALU, adder, APB | 5/5 PASS |
| Gate-level counter | 12 std cells + SDF | PASS (17 cycles) |
Internal Validation (not shipped)
| Test Suite | Result |
|---|---|
| 7 peripheral IPs (Timer, GPIO, SPI, PWM, SENT, CAN-FD, UART) | 145/152 (95.4%) |
| Ibex RISC-V CPU | 13-cycle boot verified |
| 71 unit tests | 100% pass |
| 93 IEEE compliance tests | 100% pass |
| 46 RISC-V ISA architecture tests | 100% pass |
| 152/171 blind audit assertions | 88.9% pass |
============================================== FSiMX Independent Audit, Example Suite ============================================== --- Verilog Basic --- counter FSiMX: PASS iverilog: PASS alu FSiMX: PASS iverilog: PASS fsm FSiMX: PASS iverilog: PASS --- SystemVerilog --- sv_always FSiMX: PASS iverilog: PASS sv_pkg FSiMX: PASS iverilog: PASS sv_queue FSiMX: PASS iverilog: PASS (all 11 checks) --- OpenCores --- picorv32 FSiMX: PASS iverilog: PASS (272 transactions) --- UVM Tests --- uvm_fifo FSiMX: PASS uvm_spi_master FSiMX: PASS uvm_alu_pipeline FSiMX: PASS ============================================== SCORECARD ============================================== Total: 29 PASS: 29 FAIL: 0 Rate: 100% ==============================================
5. What Does Not Work Yet
Same honesty approach as our EQWAVE and DFT posts. These are real limitations.
Known Gaps
Full UVM 1.2: Basic phases work. Full coroutine model for sequences with delays is incomplete.
Complex SV constructs: Virtual method dispatch, parameterized interfaces, nested packed/unpacked structs fail on non-trivial designs.
Performance at scale: FSiMX interpreter is in the same class as Icarus Verilog. It is significantly slower than commercial compiled simulators on large designs.
Arbitrary third-party RTL: Untested designs will hit unsupported constructs. There are 19 known blind audit failures documented in the release notes.
We are not hiding these. They are in the README.
6. Roadmap
| Priority | What | Why |
|---|---|---|
| 1 | Expand SystemVerilog construct coverage | Close the 19 known blind audit gaps |
| 2 | Full UVM coroutine model | Real sequences with delays and objections |
| 3 | Custom SV parser | Reduce external dependency on Slang |
| 4 | Compiled simulation backend | IR to C++ to gcc to native speed |
| 5 | Coverage engine | Line, toggle, branch, FSM coverage |
| 6 | Performance scaling | 100K+ instance designs |