DDI (Neural Display Driver)

RISC-V Solution

Learned per-pixel correction, right in the pixel pipeline

The DDI is a display driver IC that pairs with the neural timing controller, placing a small RISC-V core and a tightly coupled NPU directly in the pixel pipeline so that per-pixel correction becomes a learned function rather than a fixed lookup. Because inference sits in the datapath, the correction can adapt as the panel ages, with weights that update across the panel lifetime. The part is in development as a companion to the WIOWIZ neural timing controller.

Architecture

RISC-V Control Core (boot, weight loading, panel calibration) PIXEL INPUT BUFFERING INFERENCE OUTPUT Panel Pixel Input pixel stream in Clock-Domain Crossing sync into pixel clock Line Buffer local line storage RISC-V and NPU per pixel inference Small RISC-V Core Tightly Coupled NPU Learned Correction at Pixel Rate, INT8 Per-region Weight Memory learned weights Correction Output corrected pixels Panel Drive to panel On-Chip Interconnect and SRAM (AXI4 / APB) with DMA

Clean architectural view. Every block is WIOWIZ RTL on our own RISC-V core, and internal micro-architecture is not shown.

Specifications

CategoryDisplay driver IC (neural, companion to the timing controller)
Control CPUSmall RISC-V core
AITightly coupled NPU (per-pixel, INT8)
CorrectionLearned per-pixel function, updated over lifetime
MemoryPer-region weight memory, line buffer
InterfacesPanel pixel stream in, corrected pixels out
IP ownershipWIOWIZ IP and WIOWIZ VIP
Design flowWIOWIZ in-house EDA
StatusIn development (companion to TCON)

RISC-V Architecture

A small RISC-V core plus a tightly coupled NPU sit directly in the pixel path, applying learned per-pixel correction at pixel rate with weights updated over the panel lifetime, sharing the neural approach of the WIOWIZ timing controller. The design is pure-digital and built on WIOWIZ's own RISC-V core, keeping the silicon licence-free and fully controllable from spec to sign-off with our in-house EDA.

Key Features

Learned per-pixel correction

Per-pixel correction becomes a learned function rather than a fixed lookup, applied at pixel rate.

Lifetime weight updates

Weights update across the panel lifetime so the correction adapts as the panel ages.

In-pipeline NPU

A tightly coupled NPU runs inference directly in the pixel datapath, not off to the side.

Companion to the neural timing controller

Pairs with the WIOWIZ neural timing controller to share one neural approach across the panel.

RISC-V replaces the microcontroller

A small RISC-V core takes the place of the traditional microcontroller in the driver.

In-house IP

Architected, implemented and verified with WIOWIZ EDA, WIOWIZ IP.

Applications

Display driver silicon Panel makers Paired with the neural timing controller
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