Many AI models, one die
It is a multi-model edge AI inference chip that runs many AI models on a single die. It pairs a RISC-V host with the WZ-NPU matrix engine and the VAI inference architecture for real-time inference across vision, transformer and control workloads.
Architecture
Clean architectural view. Every block is WIOWIZ IP on our own RISC-V host, and internal micro-architecture is not shown.
Specifications
| Category | Multi-model AI inference chip |
|---|---|
| Host CPU | RISC-V host |
| AI engine | WZ-NPU matrix engine with VAI inference architecture |
| Workloads | vision, transformer and control models |
| Precision | INT8 and mixed precision |
| Memory | on-chip SRAM and external DDR for model weights |
| Data movement | DMA data mover |
| I/O | PCIe, Ethernet, camera |
| IP ownership | WIOWIZ IP and WIOWIZ VIP |
| Design flow | WIOWIZ in-house EDA |
| Status | architecture |
RISC-V Architecture
A RISC-V host schedules and manages many concurrent AI models while the WZ-NPU and VAI inference engine execute them in hardware, on-chip and external memory hold model weights, and a DMA data mover keeps the engines fed. WIOWIZ IP.
Key Features
Many AI models on one chip
Multiple AI models run concurrently on a single die under RISC-V host scheduling.
Real-time vision and transformer inference
Vision and transformer workloads execute in real time directly in hardware.
WZ-NPU matrix acceleration
The WZ-NPU matrix engine accelerates model execution at INT8 and mixed precision.
RISC-V host scheduling
A RISC-V host schedules and manages the concurrent models feeding the engines.
On-chip and external model memory
On-chip SRAM and external DDR hold model weights close to the engines.
In-house IP
Architected, implemented and verified as WIOWIZ IP with our in-house EDA.